1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
A semiconductor package (a semiconductor device) includes a semiconductor chip and a wiring board on which the semiconductor chip is mounted. The semiconductor chip is provided with a bump formation surface on which protruding bumps are formed. Solder, for example, is used as a material for the bumps. The semiconductor chip is mounted on the wiring board by using the bump formation surface.
In such a semiconductor device, stress is applied to the semiconductor chip and the bumps at the time of mounting the semiconductor chip or after the mounting in some cases. For example, in a case where flux is used to form the bumps, the semiconductor chip is mounted on the wiring substrate by a heat treatment such as an IR reflow treatment. In this mounting, stress sometimes occurs due to such reason as a difference in thermal expansion coefficient between the bump portions and the other portions. Such stress may cause a bump crack or a chip crack. Thus, reduction of such stress is desired.
As a related art, Japanese Patent Application Publication No. 2007-242782 discloses a technique relating to a semiconductor device in which bumps serving as external connecting terminals are joined to a semiconductor substrate. An object of this technique is to reduce or absorb stress which the bumps receive from a mounting board and at the same time ensure stable electrical connection.
Another related art is Japanese Patent Application Publication No. 2007-142017. This patent document discloses that bumps between a chip and a wiring board are arranged in concentric circles, and have diameters changing from the center circle toward the outermost circle in order to disperse stress occurring in the circumferential portion of the chip.
In some cases, stress occurring in a bump formation surface of a semiconductor chip notably increases due to a difference in the density of bumps arranged on the bump formation surface.
FIG. 1 is a schematic view, showing an example of an arrangement of bumps 101 on a bump formation surface 102. In the example shown in FIG. 1, the bumps 101 are uniformly arranged. In this case, there is no difference in the density of the bumps, and thus stress relating to the density of the bumps occurs less.
FIG. 2 is a schematic view showing another example of an arrangement of the bumps 101 on the bump formation surface 102. In the example shown in FIG. 2, the bump formation surface 102 includes a first region 103 in which the bumps 101 are densely arranged and a second region 104 in which the bumps 101 are sparsely arranged. FIG. 3 shows a simulation result of a stress distribution which occurs at the time of mounting a semiconductor chip and after the mounting. The simulation result in FIG. 3 is obtained by use of a semiconductor chip having the bump formation surface 102 shown in FIG. 2. As shown in FIG. 3, stress occurring portions 105 occur around a border between the first region 103 and the second region 104.
Apparently, there is a problem that stress at a problematic level for a product occurs when the arrangement of the bumps 101 has a notable density difference as shown in FIG. 3.